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SI9993CS
Vishay Siliconix
Si9993
12-V VCM/Spindle Motor Driver for Large Capacity HDD
FEATURES
* 12-V Motor Supply * Blocking Schottky Diode Replaced by External Synchronous Rectifier * Spindle Motor Driver Features: - External LITTLE FOOT(R) Drivers for High Current/Power Application - Constant Off-Time PWM Current Drive Minimizing Power Dissipation - Sensorless Motor Commutation Immune to PWM Noise - Externally Controlled Start-Up/Run Function - Low-Jitter Commutation Output for External Speed Control - Level Shifting Buffer Amplifier for PWM DAC - Adjustable Output Slew Rate Control - Unique Commutation Driver Minimizing Audible Noise - Programmable Phase Advance for High Speed Motor - Speed Triggered Motor Brake for Enhanced Reliability * Voice Coil Motor Driver Features: - External LITTLE FOOT Drivers for High Current/Power Application - Low Crossover Distortion in Linear Mode (Class AB) - Selectable Constant Frequency PWM or Linear Operation - Programmable Retract Voltage Clamp - Level Shifting Buffer Amplifier for PWM DAC - Direct VCM Retract Control Input - Current Sense Output for Enhanced Servo Control - Fixed PWM Output Slew Rate Limit * System Manager Features: - Power-On Reset Generator - Adjustable System Voltage Monitor - 2.3/5.0-V5%, 150 ppm/C Reference Output for External PWM DAC - Programmable Timer for Head Retract and Spindle Brake Delay - Built-In Test Ability * 3-Wire Synchronous Serial Data Interface * Internal Registers and Address Decoding with Full Readback Capability
DESCRIPTION
The SI9993CS consists of a 3-phase brushless dc motor (spindle) PWM controller and a linear/PWM transconductance stage suitable for driving a voice coil motor (head actuator). To meet the power handling capability required for a high capacity hard disk drive, both drivers utilize external LITTLE FOOT half-bridges (Siliconix Si9942 recommended). A separate LITTLE FOOT PMOS switch (Si9430) is used as a synchronous rectifier in place of the usual Schottky blocking diode. SI9993CS is manufactured in a junction-isolated BiC/DMOS process (JIBCD15) and is available in a 64-pin SQFP package, specified to operate over the commercial (0C to 70C) temperature range.
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FUNCTIONAL BLOCK DIAGRAM
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ABSOLUTE MAXIMUM RATINGS (TA = 25C)*
Voltage Referenced to GND Pin VDD Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to 7 V VCLAMP Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . .> (VCC - 0.3 V and > (VDD - 0.3 V) to 14 V VCC, VMOT Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to 14 V AGND, DGND, PWRGND to GND . . . . . . . . . . . . . . . . . . -0.3 to 0.3 V SENA, SENB, SENC, CT, VCM+, VCM-Pin . . . . . -1.0 to VCC + 1.0 V POR, FCOM, STEPCLK, ENCOM, SYSCLK, PWMIN, PWMOUT, RESETVCM, IPCLK, IPDATA and IPENABLE pins . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD + 0.3 V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VCC + 0.3 V Maximum Current (All Input Pins) . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage Temperature (Tstg) . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70C Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W Thermal Impedance (JA) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25C/W
* Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. Device mounted on one-inch square FR4 Board.
SPECIFICATIONS
Operating Conditions:
VCC = VMOT = 12 V 10%, VDD = 5 V 10%, VREF(IN) = VREF(OUT), RSS = RSV = 0.2 1%, RSRADJ = 20 k 1%, Si9942-Si9430 LITTLE FOOT Driver, FSYSCLK = 5 MHz, TA = 0 to 70C
Limits Parameter Power Supply
Normal Operation, Serial Port Idle IDD Supply Current ICC + IMOT + ICLAMP D7D6(REG0/5) = 00, All Clocks Disabled Normal Operation No Load at VREF(OUT) With VCM Load Without VCM Load 0.2 0.02 40 25 4 1.2 0.1 65 40 6 mA
Symbol
Specific Test Conditions
Mina
Typb
Maxa
Unit
D7D6(REG0/5) = 00, All Clocks Disabled
Control Logic
Low Input Current High Input Current Low Input Voltage (All Digital Inputs) High Input Voltage (All Digital Inputs) Low Output Voltage (POR) High Output Voltage (POR) Low Output Voltage (FCOM, PWMOUT) High Output Voltage (FCOM, PWMOUT) IPDATA Setup Time to Rising IPCLK Edge Rising IPCLK Edge to IPDATA Hold Time IPDATA Clock Cycle Time IPDATA Hold for IPDATA Driver Turnaround IPCLK High and Low Time IPDATA Propagation Delay WRT IPCLK Falling Edge IPENABLE Setup Time WRT IPCLK Rising Edge IPENABLE Hold Time WRT IPCLK Rising Edge WRT IPCLK Falling Edge to Data Tri-State IIL IIH VIL VIH VOL VOH VOL VOH t1 t2 t3 t4 See Timing Diagram, Figures 1 and 2. t5 t6 t7 t8 t9 See Timing Diagram, Figures 1 and 2. 100 20 10 ns 45 100 IOUT = 4 mA IOUT = -4 mA IOUT = 2 mA IOUT = -2 mA 4.1 15 15 100 70 ns 4.1 0.4 2.0 0.4 V VIN = 0 V VIN = VDD -1 A 1 0.8
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SPECIFICATIONS
Operating Conditions:
VCC = VMOT = 12 V 10%, VDD = 5 V 10%, VREF(IN) = VREF(OUT), RSS = RSV = 0.2 1%, RSRADJ = 20 k 1%, Si9942-Si9430 LITTLE FOOT Driver, FSYSCLK = 5 MHz, TA = 0 to 70C
Limits Parameter System Manager
VDD Undervoltage Detection Threshold (High-to-Low) VDD Hysteresis VCC Undervoltage Detection Threshold (High-to-Low) VCC Hysteresis POR Time-out Delay Time from PWR Failure to POR Active POR Charging Current POR Comparator Hysteresis Adjustable Internal Spindle Brake Delay Time Internal VCM Retract Delay Time VTEST Leakage 5-V Reference Initial Power-On Tolerance 5-V Reference Drift from Initial Power-On Tolerance tspindly tvcmdly IVTEST VREF V R EF ---------------V R EF D3D2(REG1) = 01 VCLAMP = 3.0 to 13.2 V VDD = VCC = 0 V D5D4(REG1) = 01 tPOR tPOR IPOR 1.0 192 ms 8 1 4.75 VREF(IN) = VREF(OUT) (Internal Reference) IOUT = 20 mA to -2 mA -1.5 5.00 5.25 1.5 A V % PORCAP = 0.5 F 350 8.5 UVADJ Unconnected 4.500 4.625 0.05 V 9.25 0.2 500 0.8 2 650 1.0 ms S A V 10.0 4.750
Symbol
Specific Test Conditions
Mina
Typb
Maxa
Unit
VCLAMP = 3.0 V, VDD = VCC = 0 V VTEST = 10 V
VCM Driver
Transconductance Output Offset Current DAC Reference Output VCMDACIN Input Range VCMDACIN Input Bias Current Feedback Resistance 3-dB Bandwidth Class B Power Amp CMRR of Current Sense Amplifier Head Retract Voltage Clamp Short Circuit Head Retract Current Current Sense Amplifier Zero Output Voltage Current Sense Amplifier Output Gain Ratio V(IVCMS) V(IVCMS)/ V(RSV) IMOTOR = 0 D7D6(REG0) = 00, D7D6(REG5) = 11 IMOTOR = 0 D7D6(REG0) = 00, D7D6(REG5) = 11 dc Gain CM Input = 0 to VCC IMOTOR = 60 mA, D7D6(REG1) = 00 0.32 120 0.4 70 0.4 0.48 180 dB V mA Ib(L/S) RFB Internal Resistor from IVCMS to COMP1 L/S, I/S and Comp Amp 12 1.0 MHz GmVCM IOS VREF/2 IMOTOR = 1 A, D5D4(REG0) = 11 D5D4(REG0) = 11 RLOAD = 100 k +VCMDACIN or -VCMDACIN to GND 1.52 -25 2.09 0.1 1.60 0 2.2 1.68 25 2.31 V 5.0 50 nA k A/V mA
2.32
2.5
2.68
V
2.67
V/V
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SPECIFICATIONS
Operating Conditions:
VCC = VMOT = 12 V 10%, VDD = 5 V 10%, VREF(IN) = VREF(OUT), RSS = RSV = 0.2 1%, RSRADJ = 20 k 1%, Si9942-Si9430 LITTLE FOOT Driver, FSYSCLK = 5 MHz, TA = 0 to 70C
Limits Parameter Spindle Motor Driver
Transconductance Spindle Driver Input Offset Voltage Current Sense Comparator Input Bias Current PWM Constant Off-Time Stability Spindle Driver Input Bias Current BEMF Detect Input Offset Voltage BEMF Detect CM Input Range Power-Down Spindle Motor Break Threshold , Measured at VCLAMP D1D0(REG1) = 11 IB(L/S) -20 2.5 2.4 3.0 GMSPIN (Start-Up) V(SPDACIN) IB(C/S) D3/D2(REG5) = 01 3.2 IMOTOR = 1 A, D5D4(REG5) = 11 IMOTOR = 0 A, D5D4(REG5) = 11 1.44 1.60 40 2 3.4 50 20 VCLAMP 2 V 3.6 1.76 A/V mV A s nA mV
Symbol
Specific Test Conditions
Mina
Typb
Maxa
Unit
PWM Pre-Driver for LITTLE FOOT(R) (Spindle Motor)
SRADJ Voltage VSRADJ ISRADJ = -50 A 1.0 V
D2/D1(REF4) = 11
VOUT = VCLAMP - 0.4 V HSA/B/C Output High Current (OFF) IOH(HS) VOUT = VCLAMP - 3 V, Slew Controlled Range VOUT = VCLAMP - 10V -1.6 -1.6 -24
D2/D1(REF4) = 00
VOUT = VCLAMP - 3 V -13
D2/D1(REF4) = 11
HSA/B/C Output Low Current (ON) IOL(HS) VOUT = VCLAMP - 3 V, Slew Controlled Range 1.4
D2/D1(REF4) = 00
VOUT = 3 V 19 mA 1.9 1.7 5.0
D2/D1(REF4) = 11
VOUT = 0.4 V LSA/B/C Output Low Current (OFF) IOL(LS) VOUT = 3 V, Slew Controlled Range VOUT = 10V
D2/D1(REF4) = 00
VOUT = 3 V 13
D2/D1(REF4) = 11
LSA/B/C Output High Current (ON) IOH(LS) VOUT = 3 V, Slew Controlled Range -1.1
D2/D1(REF4) = 00
VOUT = 3 V -7 0.5 V
SENA/B/D and VCM Clamp Diode Voltage
VCL
Measured at IF = 20 mA and IF = -20 mA
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SPECIFICATIONS
Operating Conditions:
VCC = VMOT = 12 V 10%, VDD = 5 V 10%, VREF(IN) = VREF(OUT), RSS = RSV = 0.2 1%, RSRADJ = 20 k 1%, Si9942-Si9430 LITTLE FOOT Driver, FSYSCLK = 5 MHz, TA = 0 to 70C
Limits Parameter Symbol Specific Test Conditions Mina Typb Maxa Unit
PWM Pre-Driver for LITTLE FOOT (VCM) With Slew Rate Control
VOUT = VCLAMP - 0.4 V -1.6 -1.6 -24 VOUT = VCLAMP - 3 V, Slew Controlled Range VOUT = VCLAMP - 10V
HS Output High Current OFF
IOH(HS)
Without Slew Rate Control
VOUT = VCLAMP - 3 V -1.4
With Slew Rate Control HS Output Low Current ON
IOL(HS) VOUT = VCLAMP - 3 V, Slew Controlled Range 1.4
Without Slew Rate Control
VOUT = 3 V 3.1 mA 1.9 1.7
With Slew Rate Control
VOUT = 0.4 V VOUT = 3 V, Slew Controlled Range
LS Output Low Current OFF
IOL(LS)
VOUT = 10V Without Slew Rate Control VOUT = 3 V With Slew Rate Control
VOUT = 3 V, Slew Controlled Range
5.0
3.1
LS Output High Current ON
-1.1
IOH(LS)
Without Slew Rate Control
VOUT = VCLAMP - 3 V -1.4 10.3 2.3 V 1.3 1.7 From Low to High VCC = VCLAMP = 12 V Hysteresis From Low to High VCC = VCLAMP = 12 V Hysteresis
Upper VCM Slew Rate Threshold Lower VCM Slew Rate Threshold
VCMSRth+
VCMSRth-
VCM Linear Pre-Driver for LITTLE FOOT
HS Linear High Output Voltage HS Linear Low Output Voltage HS Linear Output High Current HS Linear Output Low Current LS Linear High Output Voltage LS Linear Low Output Voltage LS Linear Output High Current LS Linear Output Low Current VOH IOUT = 0 VOL IOH IOL VOH IOUT = 0 VOL IOH IOL VOUT = VCLAMP - 3 V VOUT = 3 V 0.7 -1.4 mA 3.1 VOUT = VCLAMP - 3 V VOUT = 3 V 1.4 -1.4 mA 3.1 VCLAMP 1.6 V VCLAMP 0.8 V
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
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PIN CONFIGURATION
PIN DESCRIPTION
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12, 13, 14, 25, 26, 34, 35, 36, 58, 64 15 16 17
Name
RESETVCM HSLSPGATE HSA LSA HSB LSB HSC LSC IPDATA GND
Type
Digital, Input Analog, Output Analog, Output Analog, Output Analog, Output Analog, Output Analog, Output Analog, Output Analog, Output Analog, Output Digital, I/O Supply
Function
Direct RESET to bit D6 of REG0. Force head retract sequence if in normal operation. Connection to gate of negative VCM high-side driver Connection to gate of negative VCM low-side driver Connection to gate of external PMOSFET used to isolate VCLAMP during emergency head retract. Connection to gate of spindle 0-A high-side driver Connection to gate of spindle 0-A low-side driver Connection to gate of spindle 0-B high-side driver Connection to gate of spindle 0-B low-side driver Connection to gate of spindle 0-C high-side driver Connection to gate of spindle 0-C low-side driver Bi-directional data path for the serial port Chip substrate ground Strobe input for data word. System commands are executed at the falling edge of IPENABLE. Clock input for the serial port Digital output of stand-alone PWM driver
IPENABLE IPCLK PWMOUT
Digital, Input Digital, Input Digital, Output
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PIN DESCRIPTION
Pin No.
18 19 20 21 22 23 24 27 28 29 30 31 32 33 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55, 56 57 59 60 61 62 63
Name
PWMIN SRADJ DGND VTEST VDD SYSCLK FCOM STEPCLK SENC SENB SENA CT POR ENCOM UVADJ IVCMS ISSISS+ SPDACIN PWMREF VCC PORCAP REFGND AGND VREF(OUT) VREF/2 ISV+ ISVCOMP1 COMP2 +VCMDACIN -VCMDACIN VCLAMP PWRGND VCM+ VMOT VCMHS+ LS+
Type
Digital, Input Analog, Input Supply Analog, I/O Supply Digital, Input Digital, Output Digital, Input Analog, Input Analog, Input Analog, Input Analog, Output Digital, Output Digital, Input Analog, Output Analog, Output Analog, Input Analog, Input Analog, Input Analog I/O Supply Analog, Output Supply Supply Analog, Output Analog, Output Analog, Input Analog, Input Analog, Output Analog, Input Analog, Input Analog, Input Supply Supply Analog, I/O Supply Analog, I/O Analog, Output Analog, Output
Function
Digital input of stand-alone PWM driver Spindle Output drive slew rate control Digital negative supply External charge storage node for spindle brake function. Also used as a manufacturer's test pin +5 V digital power supply System clock input (5Mhz) for onboard timers Commutation clock output for external speed control Clock input for spindle commutation state machine, used during spindle start-up only Input to BEMF-sense circuitry; connect to 0-C Input to BEMF-sense circuitry, connect to 0-B Input to BEMF-sense circuitry, connect to 0-A Center Tap Power-on-reset pulse for entire drive electronics Enable input for onboard commutation clock generator External Undervoltage threshold adjust VCM current sense output; signal referred to VREF/2 Negative input to spindle current sense amplifier Positive input to spindle current sense amplifier Spindle Input (from PWM DAC Out) Reference supply input for stand-alone PWM driver +12 V analog power supply for the whole chip Connect to Power-on-reset timing capacitor Critical analog ground reference Analog negative supply and ground reference Reference supply output for stand-alone PWM DAC and VCM common Reference supply output for external VCM DAC Positive input to VCM current sense amplifier Negative input to VCM current sense amplifier Connection for external VCM R/C compensation Connection for external VCM R/C compensation Positive VCM input (from +VCM DAC Out) Negative VCM input (from -VCM DAC Out) +12-V digital power supply for spindle PWM section; also, inductive flyback clamp and emergency head retract power supply Ground return referred to external VCM n-channel FETs; used to power VCM class AB stage. Feedback from the positive output of VCM driver +12-V power supply referred to external VCM p-channel FETs; used to power VCM class AB stage. Feedback from the negative output of VCM driver Connection to gate of positive VCM high-side driver Connection to gate of positive VCM low-side driver
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TIMING WAVEFORMS AND TEST CIRCUIT
FIGURE 1. Read Cycle Timing Diagram
FIGURE 2. Write Cycle Timing Diagram
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FUNCTIONAL DESCRIPTION
Voice Coil Motor Driver The VCM driver provides all necessary control functions, for a linear transconductance stage, including a motor current sense amplifier, a loop compensation amplifier and a 3-A power amplifier featuring two Si9942's (external) in a full H-bridge configuration. The output half-bridge operates in the Class B mode during seeking. The track following mode is primarily a function of an onboard class AB bipolar driver. The output crossover distortion is kept to a minimum by the combined BiCMOS driver. Two external components (R3 and C3) are required to set the bandwidth of the full transconductance stage. For greater flexibility in interfacing to the external D/A converter, a DAC reference, an input level shifting amplifier and gain select are included. To minimize power dissipation of the power stage during the seek operation, the VCM driver may also be re-configured (via Bit D3/2 of REG0, see Table 2) into a constant frequency Pulse-Width-Modulated (PWM) driver. No additional external components are required for this useful option. The head retract circuitry can be activated by an undervoltage condition, an external command via serial port, or direct control via the RESETVCM pin. The retract voltage clamp is programmable from 0.4 to 1.2 V. External VCM DAC Operation The VCM driver of the SI9993CS is designed to interface to an external DAC with an output range from 0.1 V to 4.5 V and uses the internal 2.3 V as the mid-point reference (signal common). Therefore, a differential input of up to 2.2 V may be accepted. Depending on the type of DAC chosen, either VREF/2 (+2.3 V) or VREF (+5.0 V) can be used as the DAC reference. The inaccuracy of the mid-point reference may be eliminated through calibration by disabling the VCM driver [D7/D6 (REG0) = 00 or 01] and digitizing the VCM current sense output (IVCMS). The digitized value is to be stored in the ASIC or DSP as the VCM current zero scale correction factor. A differential level shift amplifier has been added between the internal 12-V current sense amplifier and the IVCMS pin such that an external ADC operating from a 5-V power supply may be used directly. Spindle Motor Driver The spindle driver powers a three-phase brushless dc motor in open drive configuration and utilizing a Hall sensor-less commutation technique. To minimize power stress on the three Si9942 (external) half-bridges, the driver operates in full time, constant off-time or variable frequency, PWM current mode. A proprietary BEMF sensing technique, consisting of a filter and a programmable EMF zero crossing comparator and an intelligent commutation delay generator, is used to derive the proper commutation zero crossing in the presence of severe PWM noise. The start-up of the motor is initiated by the microprocessor through the STEPCLK and ENCOM pins. This arrangement allows the user to tailor a start-up algorithm for any given drive. As shown in Table 2, the microprocessor may strobe the STEPCLK pin to force a new motor state sequentially. Multiple clocking will allow any undesired state to be bypassed. At an empirically determined time, the internal commutation clock generation loop may be closed by forcing ENCOM high. For complete interfacing to the microprocessor's PWM DAC, a level shifting amplifier, accepting a wide input range (via D5/D4 or REG5), is also included on chip. To minimize acoustic or EMI noise, the slew rate of the output drivers (via HSA/B/C and LSA/B/C) may be programmed by an external resistor connected through the SRADJ pin. Additional software slew rate controls are available through D2/D1 of REG4. The speed control signal from the external micro or DSP is fed to the output PWM modulator via an external DAC and the onboard buffer/level shifter. The interface is designed to work with either PWM or linear DAC. Should a PWM DAC be chosen, a stand-alone digital buffer is available to level shift the 5-V signal from the PWM timer (referred to VDD) to a supply independent signal (referred to VREF), before it is fed to the external RC low pass filter. Adaptive Commutation Delay Operation1 Inside the spindle controller of SI9993CS, the desired 30 electrical degrees (or 90 degrees for a single phase) of commutation delay is generated by sensing the motor back-emf zero crossing at the unenergized winding with a current-controlled transconductance amplifier and charging an internal capacitor to be programmable threshold with the output current of the amplifier. The delay time generated is proportional to the speed of the motor because the charging current is derived from a motor frequency to current converter. This proprietary analog timing generator, combined with the external low-pass filter (three 200-k resistors), provide excellent immunity to the highly unstable PWM noise. The resulting motor once-around jitter time is comparable to that of a linear drive system. Furthermore, the highly integrated nature of the design has eliminated all external capacitors, representing a significant savings in cost and board space. For maximum flexibility, D2/D1 of REG5 may be used to program the frequency to current converter filter bandwidth. For very high performance drive, D7/D2 or REG3 programs the commutation delay threshold in both negative (phase advance up to 23.5) and positive (phase delay up to 7.5) directions.
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TABLE 1. Spindle Commutation Sequence Sequencer State
Reset* 1 2 3 4 5 6
HSA
High Low Low High High High High
LSA
Low Low Low Low High High Low
HSB
High High High Low Low High High
LSB
Low High Low Low Low Low High
HSC
High High High High High Low Low
LSC
Low Low High High Low Low Low
*Reset is the state after exiting spindle disable or brake mode.
Quiet Commutation Operation1 Included on the SI9993CS spindle driver is a unique feedback circuit which was developed to control the supply current during the current transfer from one phase of the winding to another. At the proper time of commutation, the ramping down of the previous phase is regulated to match with the ramping up of the next phase, which is fully on initially, until all current has been transferred to the next phase. This not only reduced the constraint on power supply requirements but also eliminated annoying high frequency audible noises generated from second and third harmonics of the commutation frequency. The "quiet commutation" operation is a function of PWM off-time and slew rate control. D7/D4 of REG4 may be used to optimize the circuit performance accordingly. System Manager The system manager includes power supply monitor, power-on reset timer, individual motor on/off control, system reference generator and a variety of digital delay timers targeted for PWM and head retract functions. An external 5-MHz system clock is used mainly for the spindle motor PWM timing functions. An onboard RC oscillator is used to generate the timing necessary for the emergency motor shutdown sequence. When a tight microprocessor power supply is specified, a pair of external resistors may be used to adjust the VDD undervoltage lockout value via UVADJ pin. Finally, an external capacitor is used to set up the 500-ms power-on reset pulse for the entire drive electronics. All controls from the microprocessor or DSP are communicated via a 16-bit serial port. Serial Port A 16-bit word, clocked into the serial interface port of the SI9993CS, provides the means to program basic operating conditions, control the motor configuration and to force testing conditions suitable under the production environment. The serial port is controlled by three signals IPDATA, IPCLK, and IPENABLE. The IPDATA signal is the bidirectional data line, the IPCLK signal is used as the clock to validate the data and IPENABLE enables serial port operation. This serial port can
1. Patent Applications Pending
be used with the Intel 80C196, AMD 186 processors or other synchronous serial interfaces. The serial port allows transfer of a R/W mode bit, seven bits of register address, and eight bits of data. The port is inactive when the IPENABLE line is low, and IPCLK must be high. When IPENABLE is high, the port is active and IPDATA is strobed on the rising edge of IPCLK. The first bit transferred on the IPDATA line to the SI9993CS is the R/W mode bit. As shown in Figure 1, a R/W mode bit of `1' indicates that the data shall be read from the SI9993CS. Otherwise, the data shall be written to the SI9993CS as shown in Figure 2. The next seven bits are the register address. After the transfer of the address, IPCLK must not switch for a minimum of 70 ns to allow the IPDATA line to turn around in case of a read operation. After this pause, one byte of data is transferred to or from the SI9993CS based on the R/W mode bit. Both the address and the data are transferred with the LSB first and the MSB last. IPENABLE must be lowered to deactivate the port before the next byte can be transferred. Note that SI9993CS's six command registers are NOT decoded by unique binary address. Each register is identified by a specific address bit. (i.e. an address of 111111 will access all six registers). The address and function of each command register and the definition of each bit within the register are shown in Table 2. Note that unused, or open, bits are handled differently. For write operation, the unused bits may be either 0 or 1. For read operation, the first bit to appear at the serial port is the least significant used bit of the register being read. Data appearing after the last valid bit should be ignored. As an example, the data readout sequence for REG1 in time is D2--D3--D4--D5--D6--D7--X--X. Emergency Motor Shutdown Sequence The SI9993CS executes a motor shutdown sequence whenever a valid low supply condition is detected (i.e. POR going from High to Low). The circuitry which controls events within this emergency sequence is powered by spindle motor's kinetic energy (BEMF) via the VCLAMP pin. The critical timing for various events is to be provided by an onboard RC oscillator and digital counters. The timer's value must be programmed by the external microprocessor after the IC is first powered up. Note that a similar "normal" (nominal supply) motor shutdown may be invoked by setting D7/D6 of
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SI9993CS
Vishay Siliconix
REG5 (Spindle Command) to "00" state. Individual motor shutdown operation is also possible through the serial port. Refer to Table 2 for a complete description. Immediately after detection of the undervoltage condition, all spindle drivers are turned off while the VCM's low-side drivers are turned on to stop the head from any previous movement. Additionally, all command resistors, except REG1, are reset. After a time delay, programmed by D5/D4 of REG1, the VCM's retract circuitry is turned on. The spindle drivers remained off. The head is retracted toward the inside diameter of the disk, or (VCM+ - VCM-) is positive. The voltage clamp across the VCM, or the maximum head velocity, is limited by the stored value in D7/D6 of REG1. No programmable current clamp is available on SI9993CS. The minimum short-circuited VCM retract current is 120 mA. Refer to Figure 3 for a simplified schematic. The head retract time interval, or spindle brake delay time, is programmed via bit D3/D2 of REG1. After the time-out, the VCM drivers are turned off (tri-state) and all bits of REG1 except D1/D0 are reset. The state of the spindle motor low-side drivers are determined by D1/D0) of REG1. Depending on the motor and the number of disk platters, a spindle brake at high speed (BEMF voltage of 6 V or higher) may result in a high amount of energy dissipation in the LITTLE FOOT drivers. One solution to this problem is to use a ultra-low rDS(on) LITTLE FOOT device, such as Si4544, should the dissipation limit of the Si9942 be exceeded. In which case, D1/D0 or REG1 should be programmed for immediate brake. A lower cost solution, when feasible, is to allow the motor to spin down to a lower rpm before the low-side drivers are turned on to brake the motor. In such case, the motor speed threshold, which is sensed by measuring the motor BEMF via VCLAMP voltage, is programmed using D1/D0 of REG1. (Figure 4 shows a 3-V threshold being selected.) Also, as shown in Figure 4, once the spindle brake is on, an external pre-charged capacitor connected to the VTEST pin will be switched on to maintain the gate drive to the LITTLE FOOT drivers, even if VCLAMP drops down to zero.
FIGURE 3. Simplified Retract Circuit
FIGURE 4. Simplified Spindle Brake Circuit
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SI9993CS
Vishay Siliconix
Power-Up Sequence The POR timer receives the two supply undervoltage detection outputs and combines them to form one output called PowerFailure. If PowerFailure is low, the POR output will remain low. After the power supplies are deemed safe, PowerFailure goes high and the timer is turned on which holds the POR output low for an additional 500 ms. If PowerFailure goes back low while the timer is active, the POR output must remain low and the timer must reset and wait for PowerFailure to go back high before starting again. The POR output must drop low within 1 s from when a power failure is detected. Once the POR output drops low, the timer must also reset. If the PowerFailure output drops low for less than 600 ns, then the power failure is ignored and the POR output remains high and the timer is not reset. The POR output cannot glitch at anytime. If a power failure is detected, then the POR output must stay low for a minimum of 350 ms. A minimum of 1 V of hysteresis exists at the POR comparator which monitors the timer ramp voltage. Recommended Parameter Setting Hardware Values and Register Contents
VCM
The SI9993CS contains a transconductance amplifier to drive the voice coil motor (VCM). For proper operation, this amplifier must be compensated specifically for the VCM being driven. As a first approximation, the torque constant and inertia of the VCM may be ignored although they will have some influence on the final results, especially if large. The VCM transfer function of this simplified case may be expressed in the s (Laplace) plane as:
1 ----Lv g v = --------------Rv s + -----Lv
(1)
Where
Rv = VCM resistance in ohms LV = VCM inductance in henrys s is the Laplace operator
This has a pole at -Rv/Lv. It is desirable to cancel this pole in the interest of stability. In order to do this, a compensation amplifier is cascaded with the VCM and its driver. The transfer function of this amplifier is:
1 s + ------------------- R L + C L H c = A x ---------------------------------s (2)
Spindle
In order to perform some applications testing, some of the registers should be preloaded and certain hardware values installed. These are for a first approximation on an average spindle motor and should be adjusted for the particular motor and parameters that will be used. All registers will default to 0 at power-up. The following register value exceptions should be loaded for an average motor load. For start-up: REG3 D7D0 = 00000011; 8 Phase Advance, 13-S PWM Off-Time REG4 D7D0 = 00000000; 1.4-S On-Time Blanking, 7/8 Off-Time, Slew Rate Off, Q-COM Off REG5 D2D0 = 000; 400-ns F/I Sample Time, F/I Speed-Up On After reaching speed: REG3 D7D0 = 00000001; 8 Phase Advance, 3.4-S PWM Off-Time REG4 D7D0 = 00000111; 1.4-S On-Time Blanking, 7/8 Off-Time, Slew Rate On, Q-COM On REG5 D2D0 = 110; 40-ns F/I Sample Time, F/I Speed-Up On Hardware values: Resistor from SRADJ to Ground = 20 k for approximately 1-S Slew Rate Capacitor from VREF(in) to Ground = 1 F
Where
RL = compensation amplifier feedback resistor in ohms CL = compensation amplifier feedback capacitor in farads A = compensation amplifier and driver voltage gain at high frequency
If RL x CL is set equal to Lv/Rv, then the combined open loop transconductance in siemens becomes:
Ag to = -------------s x Lv (3)
Use these values as the series combination from COMP1 to COMP2. The absolute values should be adjusted for the desired open loop gain and closed loop bandwidth desired. This has a single pole at the origin and is therefore stable when the loop is closed.
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SI9993CS
Vishay Siliconix
TABLE 2. Serial Port Definitions (Register Address = A6A5A4A3A2A1A0) Register
REG0 (xxxxxx1) VCM Command
Bit No.
D7/D6
Name
VCM Control
Function
VCM Enable/Disable Control: "00" = All VCM amplifiers unbiased except those of current sense. VCM output drivers in tri-state. "01" = All VCM amplifiers unbiased except those of current sense. VCM brake always on. "10" = All VCM amplifiers unbiased except those of current sense. Motor shutdown sequence commences with head brake for a period of Tvcmdly, followed by head retract for a period of Tspindly. The VCM returns to tri-state thereafter. Note that this command has no effect on the spindle motor operation, or the content of REG5. "11" = VCM fully enabled for normal operation. VCM Transconductance Select (A/V): "11" = 1.60 "01" = 0.40
D5/D4
Gmsel(vcm)
"10" "00"
= =
0.80 0.10
D3/D2
VPWMsel
VCM Output State Linear/Constant Frequency PWN Select: "00" = Output operates as a class AB, linear amplifier "01" = Output operated in PWM voltage mode at 31.25 kHz "10" = Output operated in PWM voltage mode at 62.5 kHz "11" = Output operated in PWM voltage mode at 125 kHz OPEN Head Retract Voltage Limit: "11" = 0.4 V "01" = 1.0 V
D1/D0 REG1 (xxxxx1x) Powerdown D7/D6
OPEN Vretract
"10" "00"
= =
0.7 V 1.2 V
D5/D4
Tvcmdly
VCM Head Retract Delay Time (from power-down detection or command): "11" = Zero Delay "10" = 4 ms "01" = 8 ms "00" = 16 ms Spindle Brake Delay Time (from power-down detection or command, tvcmdly included): "11" = Zero Delay "10" = 144 ms "01" = 192 ms "00" = 384 ms Spindle Brake Threshold Voltage Select (VCLAMP Detect): "11" = 3 V "10" = 4 V "01" = 5 V "00" = Immediate Brake FCOM Pin Configuration Option: "00000000" = FCOM (default) "10000000" = FCOM/6 All other combinations are for testing only, no user programmable parameter is available.
D3/D2
Tspindly
D1/D0
VSPBRK
REG2 (xxxx1xx) Production Test Only REG3 (xxx1xxx) Spindle Controls
D7 Thru D0
D7 Thru D2
Vth1
Spindle Commutation Delay Adjust in Sign-Magnitude:
The value programmed controls the motor commutation delay, in electrical degree, from the last BEMF zero crossing via a 6-bit DAC. Each LSB corresponds to 1/2 electrical degree.
"011111" : "010000" : "000001" "000000" "100001" : "110000" : "111111" D1/D0 Tspinpwm = = = = = = = = = = = 7.5 Delay : 0 Neutral : 7.5 Advance 8 Advance, 8.5 Advance : 16 Advance : 23.5 Advance
"100000"
=
8 Advance
Spindle Constant Off-Time (fSYSCLK = 5 MHz): "11" = 13 s "10" "01" = 3.4 s "00"
= =
6.6 s 1.8 s
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SI9993CS
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TABLE 2. Serial Port Definitions (Register Address = A6A5A4A3A2A1A0) (Continued) Register
REG4 (xx1xxxx) Driver Controls
Bit No.
D7/D6
Name
Tblank(on)
Function
PWM On-Time Blanking Pulse Adjust (FSYSCLK = 5 MHz) "00" = 1.4 s "01" = 1.8 s "10" = 0.6 s "11" = 1.0 s PWM Off-Time Blanking Pulse Ratio: "00" = (80 to 88%) of Selected PWM Off-Time "01" = 3/4 (80 to 88%) of Selected PWM Off-Time "10" = 1/2 (80 to 88%) of Selected PWM Off-Time "11" = (80 to 88%) of Selected PWM Off-Time VCM Output Slew Rate Control Option: "0" = No slew rate limit at outputs --> "1" = Slew rate limit enabled --> Spindle Output Slew Rate Control Select: "00" = No slew rate limit at outputs --> "01" = Slew rate limit enabled --> T(p-ch) = T(n-ch) 0.1 s T(p-ch) = T(n-ch) 1 s
D5/D4
Tblank(off)
D3
VCMsr
D2/D1
SPINsr
T(p-ch) = T(n-ch) 0.1 s T(p-ch) = 0.5 x T(SRADJ) T(n-ch) = T(SRADJ) "10" = Slew rate limit enabled --> T(p-ch) = T(SRADJ) T(n-ch) = 0.5 x T(SRADJ) "11" = Slew rate limit enabled --> T(p-ch) = T(SRADJ) T(n-ch) = T(SRADJ) Note: T(SRADJ) = Rise or fall time set by resistor at SRADJ pin.
D0 REG5 (x1xxxxx) Spindle Command D7/D6
QCOM Spindle Control
Quiet Commutation (low torque ripple) Option Spindle Motor Enable/Disable Control: "00" = Spindle amplifiers unbiased and state machines reset. Spindle output drivers in tri-state. "01" = Spindle amplifiers unbiased and state machines reset. Spindle motor brake always on. "10" = All amplifiers unbiased and state machines reset. Motor shutdown sequence commences with tri-state output for a period of Tvcmdly, followed by spindle brake. Note this command will force a head retract, but will not affect the content of REG0. "11" = Spindle drivers fully enabled for normal operation. Spindle Transconductance Select (A/V): "11" = 1.60 "01" = 0.40
D5/D4
Gmsel(spin)
"10" "00"
= =
0.80 0.10
D3
Direct PWM
STEPCLK Pin Function Select: "1" = Direct PWM Input (steady running state only) "0" = Start-up step clock Commutation F/I Sample Time: "00" = FCOM/12 400 ns "10" = FCOM/102 50 ns F/I Speed-Up Circuit Select: "0" = On "1" = Off
D2/D1
(F/I)tsample
"01" "11"
= =
FCOM/38 133 ns FCOM/128 40 ns
D0
(F/I)spdup
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SI9993CS
Vishay Siliconix
APPLICATIONS
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